What is Microblaze Processor : Architecture, Working & Its Applications

The MicroBlaze processor was developed in 2002 to integrate several complicated features to meet new as well as growing market demand. So, the MicroBlaze processor is an essential element within the Low-End Portfolio of Xilinx to enable faster system development which contains Artix®-7 FPGAs, Spartan®-6, Zynq®-7000 AP SoCs. This processor is extremely configurable, so it can be used as an embedded processor or microcontroller within FPGAs and also used as a co-processor in the Zynq-7000 AP SoCs based on ARM Cortex-A9. This article gives brief information on MicroBlaze processor – architecture and working with applications.


What is Microblaze Processor?

The soft microprocessor which is designed mainly for FPGAs of Xilinx is known as the MicroBlaze processor. This processor is simply implemented within the general-purpose memory & logic fabric of FPGAs of Xilinx. This processor is similar to the DLX architecture based on RISC and it has a flexible interconnect system so that it supports different embedded applications. The main I/O bus and the AXI interconnect of the MicroBlaze is a memory-mapped transaction bus with a master-slave facility.

MicroBlaze utilizes a dedicated LMB bus to access local memory & provides quick on-chip storage. Many parts of this processor can be user configured like the size of the cache, depth of pipeline memory management unit, embedded peripherals & bus interfaces.

Microblaze Features

The features of Microblaze include the following. It has 32 general purpose registers.

  • It has 32-bit instruction words including 2 addressing modes & 3 operands.
  • The address bus is 32-bit.
  • It has 3 stage pipeline or a 5-stage pipeline.
  • An ALU block unit with a shifter.
  • Harvard architecture includes 32-bit data and address bus.
  • Data interface & LMB or local memory bus instruction.
  • AX14 and AX14 stream interfaces.
  • Floating point unit & memory management unit.
  • It supports lockstep.
  • Debug & trace interface.

Microbaze Architecture

The block diagram of the MicroBlaze processor is shown below. This MicroBlaze processor is extremely customizable and it supports above 70 design options. This architecture shows permanent hardware features as well as configurable options like the Instruction or Data Cache, the Memory Management Unit, the Floating Point Unit, etc.

An embedded system assembled around a MicroBlaze processor mainly includes MicroBlaze Soft Processor Core, On-chip Local Memory, Standard Bus Interconnects, and OPB Peripherals (On-chip Peripheral Bus). A MicroBlaze processor system mainly ranges from a core of processor by a local memory to a large system including several MicroBlaze processors, external memory & many OPB peripherals.

Microblaze Processor Architecture
Microblaze Processor Architecture

Soft Processor Core

The soft processor core of MicroBlaze is central to the MicroBlaze embedded system. This is a very fast and efficient 32-bit RISC processor which has the following features.

  • The instruction set is Orthogonal.
  • Separate data & instruction buses.
  • 32-bit general purpose registers.
  • It has an optional complete 32-bit barrel shifter.
  • Inbuilt interfaces to fast OCM or on-chip memory & IBM’s industry-standard OPB (On-chip Peripheral Bus).

Implementations within Virtex-II and afterward devices support multiply of hardware.

On-chip Local Memory

The synchronous memory is a local memory that is mainly used for allowing on-chip Block RAM.

Standard Bus Interconnects

The bus interfaces at the instruction & data side include an interface to local memory which is called LMB (Local Memory Bus) & an interface to the On-chip Peripheral Bus of IBM. So we can design systems that strictly stick to Harvard architecture, otherwise, to share resources, we can utilize a single OPB within combination through a bus arbiter.

The local memory bus gives assured single-cycle entrée for on-chip block RAM. This is a very efficient, simple, and single-master bus protocol and it is perfect for interfacing fast local memory. The OPB or On-chip Peripheral Bus is a 32-bit broad multi-master bus that is perfect for uniting peripherals & exterior memory to the core of the MicroBlaze processor.

On-chip Peripheral Bus Peripherals

The MicroBlaze hardware system is completed by OPB peripherals to provide different functions like Watchdog Timer or Timebase, General purpose Timer or Counters, IC (Interrupt Controller), different controllers like SRAM, Flash Memory, ZBT Memory, BRAM, DDR, SDRAM, UART Lite, SPI, I2C, General purpose I/O, UART 16450/550 and Ethernet 10/100 MAC. Additionally, we can also add & define peripherals mainly for custom functions, otherwise, an interface to a design that exists in the FPGA.

Microblaze Instruction Set

Microblaze instruction sets are arithmetic, logic, branch, load/store, and others. The size of all the instructions is fixed. At most 3-registers can be given as operands. Microblaze includes two instruction formats Type A and Type B which are shown below.

Type A instruction format is mainly used for register-register instructions. So it includes the opcode, single destination & two source registers. Type B instruction format is mainly used for register-immediate instructions which include the opcode, single destination, and single source registers.& a 16-bit immediate value source.

Instruction Formats
Instruction Formats

In the above two instruction formats, the opcode is an operation code, Rd is a destination register that is encoded with 5-bits, Ra & Rb are source registers where each encoded with 5-bits and Immediate is a 16-bit value.

Arithmetic Instructions

The type A and Type B arithmetic instructions are given below.

Type A

ADD Rd, Ra, Rb

add

Rd = Ra+Rb, Carry flag affected

ADD K Rd, Ra, Rb

Add and keep carry

Rd = Ra+Rb, Carry flag not affected

RSUB Rd, Ra, Rb

Reverse subtract

Rd = R-Rb, Carry flag not affected

Type B

ADD I Rd, Ra, Imm

add immediate

Rd = Ra+signExtend32 (Imm)

ADD IK Rd, Ra, Imm

add immediate and keep carry

Rd = Ra+ signExtend32 (Imm)
RSUBIK Rd, Ra, Imm

reverse subtract with immediate

Rd = Ra+ signExtend32 (Imm) -Ra

SRA Rd, Ra

arithmetic shift right

Rd = (Ra>>1)

Logic Instructions

The type A and Type B logic instructions are given below.

Type A

OR Rd, Ra, Rb

Logical or

Rd = Ra | Rb

AND Rd,Ra,Rb

Logical add

Rd = Ra & Rb
XOR Rd, Ra, Rb

Logoical xor

Rd = Rb ^ Rb

ANDN Rd, Ra, Rb

Logical and not

Rd = Ra & (Rb)

Type B

ORI  Rd, Ra, Imm

logical OR with immediate

Rd = Ra | signExtend32 (Imm)
ANDI  Rd, Ra, Imm

logical AND with immediate

Rd = Ra & signExtend32 (Imm)
XORI  Rd, Ra, Imm

logoical XOR with immediate

Rd = Ra ^ signExtend32 (Imm)

ANDNI Rd, Ra, Imm

Logical AND NOT with immediate

Rd = Ra & (signExtend32 (Imm))

Branch Instructions- Unconditional

Modify the Program Counter register

BRID  Imm

branch immediate with immediate delay

PC = PC+ signExtend32 (Imm)

allow delay slot execution

BRLID Rd, Imm

branch and link immediate with immediate delay (function call)

Rd = PC

PC = PC+& signExtend32 (Imm)

allow delay slot execution

RTSD  Ra, Imm

return from subroutine

PC = Ra + signExtend32 (Imm)

allow delay slot execution

RTID Ra, Imm

return from interrupt

PC = Ra + signExtend32 (Imm)

allow delay slot execution

set interrupt enable in MSR

 Branch Instructions- Unconditional1

Change the Program Counter register when a condition is satisfied

BEQI  Ra, Imm

branch if equal

PC = PC+ signExtend32 (Imm)

If Ra = = 0

BREI Ra, Imm

branch if not equal

Rd = PC

PC = PC+& signExtend32 (Imm)

If Ra! = 0

Branch Instructions- Unconditional2

Change the Program Counter register when a condition is satisfied

BLTI  Ra, Imm

branch if lower than

PC = PC+ signExtend32 (Imm)

If Ra < 0

BLEI Ra, Imm

branch if lower equal than

Rd = PC

PC = PC+& signExtend32 (Imm)

If Ra!< = 0

BGTI Ra, Imm

branch if greater than

PC = PC+ signExtend32 (Imm)

If Ra!> 0

BGEI Ra, Imm

branch if greater equal than

PC = PC+signExtend32 (Imm)

If Ra!>= 0

 Load/Store Instructions -Type A

LW Rd, Ra, Rb

Load word

Address = Ra+Rb

Rd = *Address

SW Rd, Ra, Rb

Store  word

Address – Ra+Rb

*Address = Rd

Type B

LWI  Rd, Ra, Imn

Load word immediate

Address = Ra + signExtend32 (Imm)

Rd = *Address

SW Rd, Ra, Imm

Store  word immediate

Address = Ra + signExtend32 (Imm)

*Address = Rd

Other Instructions

IMM, Imm

immediate

Extend the Imm of a preceding type B instruction to 32-bits.
MFS Rd, Sa

Move from special purpose register

Rd = Sa

Sa- special purpose register, source operand

 

MTS Sd, Ra

Move to special purpose register

Sd = Ra

Sd – special purpose register, destination operand

 Registers

The architecture of the MicroBlaze processor is completely orthogonal which includes 32-bit general purpose registers & 32-bit special purpose registers like Program Counter & Machine Status Register.

Pipeline Architecture

MicroBlaze utilizes a 3-stage pipeline architecture including fetch, decode, & complete stages. Automatically, the data forwarding, branches & pipeline stall are determined within the hardware.

Load or Store Architecture

MicroBlaze supports memory in three data sizes 8 bits (Byte), 16 bits (Halfword) & 32 bits (Word). So, memory accesses are data-size aligned always. This is a Big-Endian processor which uses the address of the Big-Endian address as well as labeling conventions once accessing memory.

Interrupts

Once an interrupt takes place, then this processor will end the present execution to manage the interrupt request through branching to interrupt vector address & store the instruction address that needs to be executed. This processor will stop future interrupts by clearing the IE (Interrupt Enable) flag within the MSR (Machine Status Register).

How Does Microblaze Work?

The MicroBlaze processor supports 32-bit bus width and this processor core is a RISC-based engine that includes a register file based on 32-bit LUT RAM through separate instructions for memory & data access.
This processor simply supports both on-chip BlockRAM & external memory. Similar to the IBM PowerPC; all peripherals utilize the similar CoreConnect OPB bus so; the peripherals of the processor are well-matched with PowerPC on Virtex-II Pro.

The MicroBlaze processor delivers complete flexibility to choose the combination of memory, peripheral & interface features that will provide you with the precise system that you require on a single FPGA with less cost.

Difference B/W Microblaze Vs Risc-V

The difference between MicroBlaze and RISC v include the following.

Microblaze

Risc-V

It is a soft microprocessor core mainly designed for Xilinx FPGA.

 

RISC-V is an instruction set architecture rooted in RISC principles.

 

It uses Harvard RISC architecture. It uses instruction set architecture.
Its license is proprietary (Xilinx) Its license is open source.
The depth of the pipeline is 3 or 5. The depth of the pipeline is 5.
Its performance is 280 DMIPs. Its performance is 250 DMIPs.
Its speed is 235 MHz. Its speed is 250 MHz.
It has 1027 LUTs. It has 4125 LUTs.
The implementation of technology used is Xilinx FPGA. The implementation of technology used is FPGA/ASIC.

Microblaze Advantages

The advantages of MicroBlaze include the following.

  • It is economical.
  • It is highly configurable.
  • Its performance is high as compared to ARM.
  • It is supported by an embedded development kit.
  • It is a soft microprocessor core.
  • To assist you quickly arranging your application, this processor includes three fixed configurations which are related to well-known processor classes microcontroller, real-time, and application processor.

Microblaze Applications

The applications of MicroBlaze include the following.

  • This processor meets many different application requirements like Industrial, Automotive, Medical & Consumer, etc.
  • The applications of MicroBlaze range from simple state machines based on software to complex controllers used in embedded applications or Internet-based appliances.
  • It is optimized for embedded applications like industrial control, office automation & automotive.
  • The MicroBlaze is capable of communicating with a large set of peripherals to fit in medium-scale applications.
  • The soft nature of this processor makes it customizable for different applications where designers can exchange features for size to meet price & performance goals for medical, automotive, industrial & security applications.

Thus, this is all about an overview of the Microblaze processor. This is a fully featured, 32-bit programmable RISC soft processor core. This processor meets different requirements within different fields like consumer, medical, industrial, automotive & communications infrastructure markets. It is extremely configurable, so used as the embedded processor or microcontroller within FPGAs otherwise like a co-processor for the ARM. Here is a question for you, what is FPGA?

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