# Up/Down Counter : Working, Circuit, IC74193 Pin Out & Its Applications

In digital logic & computing, a sequential circuit that is used to count pulses is called a counter. A counter is a set of FFs including an applied CLK signal and this is the broad application of FFs. These are designed as separate ICs (integrated circuits) to use extensively in digital circuits and also in larger ICs. Counters are available in different types like Johnson counter, asynchronous or ripple, synchronous counter, decade, ring, and Up/Down counter. So, this article discusses one of the types of counter namely an Up/Down counter-theory – working with applications.

## What is an Up/Down Counter?

The up/Down counter is also known as the bidirectional counter which is used to count in any direction based on the condition of the input control pin. These are used in different applications to count up from zero to provide a change within the output condition on attaining a fixed value & others count down from a fixed value to zero to give an output condition change. There are some types of counters like TTL 74LS190 & 75LS191 which can function in both up & down count mode based on the condition of an input pin of up/down count mode.

### Up/Down Counter Circuit

The circuit diagram of the 3-bit up/down counter is shown below. This circuit is designed with flip-flops. In the up counter, every flip-flop is activated through the normal o/p of the previous FF (from ‘Q’ o/p of primary flip-flop to the next FF’s CLK); while in a down-counter, every flip-flop is activated through the complement o/p of the previous FF (from the output of first FF to CLK of next FF).

#### Up/Down Counter Working

The up/down counter operation can be controlled through the control input of up-down. This up/down counter works in two modes like count up mode and countdown mode. The tabular forms of count up and countdown are shown below.

The count-up mode tabular form is shown below.

 States QC QB QA 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1

The count-down mode tabular form is shown below.

 States QC QB QA 7 1 1 1 6 1 1 0 5 1 0 1 4 1 0 0 3 0 1 1 2 0 1 0 1 0 0 1 0 0 0 0

As we know that for the operation of up/down counting, sometimes the previous flip-flop needs input from Q output of the primary flip-flop to CLK of next FF for up-counting & sometimes from Q^ output of primary FF to CLK of next FF for down-counting. Generally, a FF can hold 1- bit so for a three-bit operation, it needs 3 FFs.

In the above circuit, an inverter is connected among the two control lines like count up and countdown to make sure that the count-up & count-down cannot be in the HIGH condition at the same time.

Once the count-up or countdown line is held HIGH, then AND gates at the lower side will be disabled so their o/p will be zero. As a result, they will not change the OR gate outputs. Simultaneously the higher AND gates will be enabled. Thus, ‘QA’ will supply throughout the OR gate as well as into the B flip flops CLK input. Likewise, ‘QB’ will be gated into the CLK input of the C FF. So, once the input signals are applied, then it will count up & follow a normal binary counting series from 000 -111.

In the same way, once the count-up or countdown line is held LOW, then upper side AND gates will be disabled & the lower side AND gates will be enabled by allowing both the Q′A & Q′B to flow throughout the CLK inputs of the FF’s. Thus in this state, this counter will start counting in down mode, when the i/p pulses are applied.

#### How does the Up/Down Counter Count a Clock Pulse?

In up counter, it starts counting from low to high whereas in a down counter, it starts counting from high to low. In an Asynchronous 3-bit up/down counter, the counter outputs are taken from the FFs complement outputs like Q′ instead of from the normal o/ps for every flip-flop. The starting count series is QA QB QC => 111. Every negative edge of the CLK ‘QA’ toggles its condition. Likewise, with every negative transition of the QA’ output, the QB’ output toggles & the same thing takes place for QC’. Therefore the count series goes on reducing from 7 to 0 and so on through every clock pulse.

In the up counter, every flip-flop is activated through the normal o/p of the previous FF (from ‘QA’ o/p of primary flip-flop to the next FF’s CLK); while in a down-counter, every flip-flop is activated through the complement o/p of the previous FF (from the output of first FF QA’ to CLK of next FF).

In the up counter, the first flip flop is connected to logic 0, so, it will toggle for each falling edge.
The input of the second flip flop is connected to the first FFs ‘QA’, then it will change its condition once QA = 1 & there is a falling clock edge.

Likewise, the third flip flop is connected to the second FFs ‘QB’ then it changes its state when QB = 1 and there is a falling clock edge. Through this, we can produce up counter’s counting states. After each eighth falling edge, again the counter will reach to 0 0 0 state.

In the down counter, the first flip flop is connected to logic 1 then it will toggle for each falling edge.
The input of the second flip flop is connected to the first FFs QA’ then it will change its condition once QB’= 1 & there is a falling clock edge.

Likewise, the third FF is connected to the second FFs QB’ then it will change its condition once QB’= 1 and there is a falling edge of the clock. Through this, simply we can produce down counter’s counting states. After each eighth falling edge, again the counter reaches to 0 0 0 state.

### Up/Down Counter IC

The Up/Down counter IC like 74193 IC is a 4-bit. synchronous Up/Down MODULO-16 binary counter. This IC includes two CLK input pins which are used to count up & count down the fixed value, so the o/p is synchronous through the CLK inputs.

The separate Count Up & Count Down terminals are used for higher counter designing or cascading this up/down counter IC. The master reset pin is used to reset the entire chip and also an active low parallel load i/p pin is used to begin counting through any number.

#### IC 74193 Pin Configuration

The IC 74193 includes 16-pins where each pin and its function are discussed below.

• Pin1 (CLR): This is an active-low clear i/p.
• Pin2 (CLK): This is a clock i/p signal.
• Pin3 (A (LSB), Pin4(B), Pin5 (C) & Pin6 (D(MSB): These pins are preset i/ps to load data.
• Pin7 (ENP): This is an active-high i/p ENP.
• Pin8 (GND): This is a Ground pin.
• Pin10 (ENT): This is an active-high ENT i/p pin.
• Pin11(Qd(MSB)), Pin12(Qc), Pin13 (Qb) & Pin14 (Qa(LSB)): These pins are outputs of Flip-Flops.
• Pin15 (RCO): This is a ripple carry o/p logic from 0 – 1).
• Pin16 (Vcc): This is the power i/p pin.

### Features

The features of IC 74193 include the following.

• Its CLK frequency is 32MHz.
• Its power dissipation is 93mW.
• 4-Bit Modulo-16 Up/Down counter.
• Preset i/ps are obtainable.
• It is programmable synchronously.
• Internal ripple carries for quick counting.
• Carry o/p for n bit cascading.
• The propagation time is 14ns.

#### Up/Down Counter using IC 74193

The up/down counter using IC74193 is shown below. The circuit is connected as shown in the following diagram. In the circuit, the Vcc is connected to pin-16 and the clear pins are grounded. The inputs in the circuits are given through pins 15, 10, 1, and 9 (PA, PB, PC, PD). The outputs pins are 3,2,6 & 7 (QA, QB, QC, QD). The input pin of the inverter is connected to pin12 (carry) whereas its output pin is connected to the load of IC or pin11.

In the circuit diagram, pin5 is connected to clock up & pin4 is connected to clock down. Once the pin4 is made high then the up/down counter will count in down mode. When the pin5 is made high then this counter count is in an up mode. So, this 74193 IC is used as a MOD Up/Down N counter.

#### Difference between Up and Down Counter

The difference between the up and down counter includes the following.

 Up Counter Down Counter Up counter counts from ‘0’ to the highest number of counts. Down counter counts from the highest value to the ‘0’ value. It counts events in increasing order. It counts events in decreasing order.

The advantages of an up/down counter include the following.

• The up/down counter can be cascaded within the high-speed mode.
• This counter can be synchronously incremented or decremented based on the CLK transition from low to high.
• These counters are very easily designed with flip-flops.

The disadvantages of up/down counter include the following.

• These counters are not widely used because they are inaccurate at high clock speeds.
• For re-synchronization, an additional FF is necessary.
• The counting errors may happen for high CLK frequencies because of propagation delay.
• These counters have a very large propagation delay when counting large no. of bits.

### Applications

The applications of up/down counter include the following.

• This type of counter can be utilized as a self-reversing counter.
• This counter can also be used as a clock divider circuit.
• This type of counter is used in car parking slots.
• These counters are used for low noise emission and low power applications.
• These are used as frequency dividers.