# What is Binary Multiplier : Working & Its Applications

In digital systems, combinational logic circuits such as a binary multiplier, binary adder, binary subtractor, and binary division are used to perform binary arithmetic operations like multiplication, addition, subtraction, and division of two binary numbers ‘0’ and ‘1’. These are widely used in various applications like computers, mobiles, calculators, general-purpose processors, and digital signal processors to process the signal with various algorithms. This article gives a brief description of the types, rules, and methods involved in the binary multiplier for binary multiplication.

## What is Binary Multiplier?

A binary multiplier definition is; an electronic device or digital device or a combinational logic circuit that performs the multiplication of two binary numbers (0 and 1). The two binary numbers or the two binary inputs used in the binary multiplication are multiplicand and multiplier to get the binary product as a result.

The bit size of the multiplier and the multiplicand can be varied. But the bit size of the binary product depends on the multiplier and the multiplicand bit size. The sum of the multiplier and the multiplicand bit size is equal to the final binary product’s bit size.

### Function of Binary Multiplier

In the first step of the process of the binary multiplier, the partial product terms are obtained by the bit by bit multiplication, which is equal to the ANDing of two binary numbers. In the next step, all the partial product terms of each column are added together to get the final binary product output.

The logic circuit design of this multiplier varies with bit size and its complexity increases with an increase in the multiplier’s bit size. It is governed by the AND gate functions when the two bits, which are to be multiplied, are fed as inputs with various bit sizes.

The main function of this multiplier is to do binary multiplication of 2 binary numbers with various bit sizes and reduce the calculation time in electronic digital systems such as computers. The binary multiplication is similar to the decimal multiplication.

#### Rules of Binary Multiplier

Like other binary operations, this multiplier involved in binary multiplication is much easier and similar to decimal multiplication. There are multipliers and multiplicands. The result of the multiplication gives the product. It performs binary multiplication of binary numbers (0 and 1) only, so you only need to multiply 0 and 1. The following are the rules of binary multiplier for binary multiplication.

Rule 1: 0 × 0 = 0

According to this rule, the binary product of zero is itself equal to zero. So the binary product of zero and zero is zero.

Rule 2: 0 × 1 = 0

The binary product of zero and one is zero.

Rule 3: 1 × 0 = 0

The binary product of one and zero is zero.

Rule 4: 1 × 1 = 1 ( Carry or borrow in not applicable)

The binary product of one and one is one

#### Truth Table

The binary multiplier truth table is given below.

 Input A (Multiplicand) Input B (Multiplier) Output C  (Binary Product) 0 0 0 0 1 0 0 0 0 1 1 1

### Binary Multiplier Types

The following are the binary multiplier types.

1) 2×2 Binary multiplier or 2-bit multiplier.
– 2-bit multiplier using 2-bit full adder.
– 2-bit multiplier using individual single-bit adders.
2) 3×3 binary multiplier or 3-bit binary multiplier.
– 3-bit binary multiplier using 3-bit full adders.
– 3-bit binary multiplier using single-bit adders.
3) 4×4 binary multiplier or 4-bit multiplier.
– 4-bit binary multiplier using 4-bit full adders.

#### 3×3 Binary Multiplier

A 3×3 binary multiplier is one of the combinational logic circuits, which can perform binary multiplication of two binary numbers having a bit size of a maximum of 3 bits. The bit size of the resultant output binary product is 6.

Consider the multiplicand A0 A1, A2 and the multiplier B0, B1, B2, and the final binary product output as P0, P1, P2. The 3 partial product terms are obtained in the binary multiplication because it is a 3-bit multiplier. This 3×3 multiplier can be implemented using a 3-bit full adder and individual single-bit adders. Consider the logical circuit design of the 3-bit multiplier using 3-bit full adders as shown in the figure below.

A2 A1 A0 (multiplicand)
X B2 B1 B0 (multiplier)
——————————————
A2B0 A1B0 A0B0
A2B1 A1B1 A0B1 X
A2B2 A1B2 A0B2 X X
———————————————
A2B2+C+C A2B2+A1B2+A2B2+C+C A1B1+C+A0B2+A2B0 A0B1+A1B0 A0B

The carry bit is raised when A2B0 and A1B1 are added together. By the addition of the sum obtained from that, the carry bit is obtained from the addition of A0B1 and A0B2 to A1B0, which can raise another carry bit. Hence 2 carry bits are obtained and carried over for the addition of A2B1 and A1B2 and the 2 more carry bits are generated in the same way.

This method is very simple when compared to other methods. The circuit is designed with 3-bit full adders to add the 3 partial product terms. The least significant bit (LSB) of the 1st partial product is not added to the next partial product because it is taken as an LSB of the final binary product output obtained.

From the above logical circuit, one 3-bit full adder is used to add the first 2 partial products together and the other 3-bit full adder adds the 3rd partial product with the sum of the first adder.

The number of AND gates required for the circuit design are determined from the formula m*n, where ‘m’ is multiplier bits and the ‘n’ is multiplicand bits. The number of adders required is determined by the formula (m-1) to produce m+n bits. So, this 3-bit multiplier requires 9 AND gates and two 3-bit full adders.

When the three partial product terms are added together, the LSB of the sum of each 3-bit full adder is directly taken as the output and the remaining 3-bits are added to the next partial product.

#### Binary Multiplier using Shift Method

As an alternative to the parallel binary multiplier circuit, a manual multiplication method can be implemented using an n-bit adder, 4 registers (A, B, C, and Q), offset, and control logic as shown below block diagram.

In this method, the 4-bit multiplier is stored in the Q register, the 4-bit multiplicand is stored in the B register, and the A register is initially set to zero. The multiplication process starts by checking if the LSB (least significant bit) of the number B is 0 or 1.

If B0 = 1, the number in the multiplicand (B) is added with the LSB of register A, and all bits in registers C, A, and Q are slightly shifted to the right by one bit.

If bit B0 = 0, the combination of registers C and Q is shifted to the right by one bit without any additional process. This process is repeated n times for n bits. This binary multiplication method is called parallel multiplication using the shift method or binary multiplier using the shift method.

Consider the figure below, where the values of multiplier and multiplicand are shown as 1011 and 1101, which are loaded into the registers Q and A, respectively. Register C is set to 0 initially, so register A is also 0, and carry is stored in addition.

Since B0 = 1, we add the number in B to the bits in A, then the addition result is 1101, and the Q and A registers are shifted 1 bit to the right so that the new values during the first cycle are 0110 and 1101. You must repeat this process 4 times to perform a 4-bit multiplication. The final result of the multiplication is available as 10001111 in registers A and Q as shown.

An unsigned 4×4 binary multiplier takes two, 4-bit inputs to produce one output of 8 bits. Similarly, an 8×8 multiplier produces an output with 16 bits by taking two 8-bit inputs. This multiplier with logic circuits is implemented on integrated circuits (ICs) with various pin configurations, used for several applications of microprocessors like controlling devices, computers, mobiles, calculators, DSPs, and many more.

### Binary Multiplier using ASM Chart

The Binary multiplier using the ASM chart (Algorithm State Machines) implements the algorithm for binary multiplication as shown in the figure below.

From the above algorithm, ‘<<‘ is indicated for assignment. For example, ‘C<<0’ means ‘C is set to 0’.

In this process 3 states like IDLE, MUL0 and MUL1 are used to provide control signals to the datapath for performing multiplication sequences. The process begins with ‘G’ input. The ASM remains in an IDLE state as long as G remains MUL0. The binary multiplication process starts when G=1. When the ASM is moved to the MUL0 state, the carry flip flop and the register A are cleared (C<<0 and A<<0), the counter is preset to n-1 (P<<n-1) and the Q register is loaded with the multiplier.

In the MUL0 state, the value of the multiplier’s each bit (available on Q0) determines whether the multiplicand is added (Q0=1) or not (Q0=0). If Q0=0, then the carry flip flop is cleared. If Q0=1, then the carry flip flop stores the Cout (carry output) obtained from the adder.

In the MUL1 state, the carry flip flop, A register, and Q register are denoted as (1+n+n) bit registers and together shifted one position to the right. In the ASM chart, this is indicated as C|A|Q<<shr (C|A|Q). Then the counter is also decremented, which is indicated as (P<<P-1). The Z values determine whether,

• Return the MUL0 state (if Z=0) for the continuation of iteration or
• Return to the IDLE state (if Z=1) to complete the process. Note that if Z=1, the counter is counted down from n-1 to 0 and hence completes the n iterations.

If the state IDLE=0, then the multiplier is indicated for ‘currently multiplying’. If IDLE=1, (ASM chart returns to IDLE=1), then it indicates that the binary multiplication process is completed.

At this point in the design process, the control signals are identified. It can be done by observing the datapath and the ASM chart. The below tabular form shows all the operations taken on each component in the datapath with the corresponding control signal names.

 Datapath Component Operation Control Signal Names Carry Flip flop C<<0, C<

#### Binary Multiplier Block diagram

The process of binary multiplication is divided into two components as datapath and the control logic/controller. This multiplier block diagram with datapath and the control logic is shown in the figure below.

The datapath is used to manipulate the data according to the requirements of the system. The control logic or the control unit or the controller is used to generate the signals for sequencing the operations in the data processor.

From the above block diagram, we can observe that,

Input Data: Multiplicand (n bits) and the multiplier (n bits)

Output Data: Binary Product (2n bits)

Control Signals of Controller or Commands: Clear carry, Load, Shift and Clear for each shift register and Initialise (for counter).

Status Conditions: Z (zero detect) and Q0 (multiplier’s each bit)

### Binary Multiplier Verilog Code

Let’s have a look at 2×2 binary multiplier Verilog code in dataflow modeling and behavioral modeling.

#### 2×2 binary multiplier in Dataflow modelling:

library ieee;
use ieee.std_logic_1164.all;

entity multiply is
port (A, B: in bit_vector(1 down to 0);
P: out bit_vector(3 down to 0)
);
end multiply;

architecture data flow of multiply is
begin
P(0) <= A(0) AND B(0);
P(1) <= (A(1) AND B(0)) XOR (A(0) AND B(1));
P(2) <= ((A(1) AND B(0)) AND (A(0) AND B(1))) XOR (A(1) AND B(1));
P(3) <= ((A(1) AND B(0)) AND (A(0) AND B(1))) AND (A(1) AND B(1));
end architecture;

#### 2×2 Binary Multiplier Verilog code in Behavioural Modelling

library ieee;
use ieee.std_logic_1164.all;
entity multiply_behav is
port (A, B:in bit_vector (1 down to 0);
P: out bit_vector (3 down to 0);
end multiply_behav;

architecture behavioural of multiply_behav is begin

process (A, B) is
begin
case A is
when “00”=>
if B=”00″ then P<=”0000″;
else if B=”01″ then P<=”0000″;
else if B=”10″ then P<=”0000″;
else P<=”0000″;
end if;

when “01”=>
if B=”00″ then P<=”0000″;
else if B=”01″ then P<=”0001″;
else if B=”10″ then P<=”0010″;
else P<=”0011″;
end if;

when “10”=>
if B=”00″ then P<=”0000″;
else if B=”01″ then P<=”0010″;
else if B=”10″ then P<=”0100″;
else P<=”0110″;
end if;

when “11”=>
if B=”00″ then P<=”0000″;
else if B=”01″ then P<=”0011″;
else if B=”10″ then P<=”0110″;
else P<=”1001″;
end if;

end case;

end process;
end architecture;

The binary multiplier advantages are given below.

• The intermediate product terms or partial product terms are generated very easily and are simple.
• It multiplies multiplicand with the multiplier of various bit sizes and the range of their bit sizes can be varied.
• It helps to reduce the time required for processing the digital signal with algorithms in signal processors.
• Available in small ICs for commercial electronic applications like computers, mobiles, calculators, and processors.
• The circuit design is simple when compared to binary adders and binary subtractors.
• Cost is low.

### Applications

The binary multiplier applications are listed below:

• Used in computers.
• Used in mobiles.
• Used in high-speed calculators.
• Used in digital signal processors.
• Used in controlling devices.
• Used in digital communication systems.

#### 1). What is a binary multiplier in VHDL?

The VHDL program for this multiplier can be written in 3 ways. They are,

• One is Dataflow modeling, which describes the data flow through every logic gate using equations.
• Behavioral modeling defines the behavior of the entity by using sequential statements
• Structural modeling describes the circuit with the help of interconnections of the individual components in the circuit.

#### 2) What is needed to implement a 2-bit binary multiplier?

The 2-bit binary multiplier is implemented by using 2 XOR gates and 6 AND gates in total or it can be implemented using 4 AND gates and 2 half adders.

Thus, this is all about an overview of a binary multiplier used in various electronic devices. Here, a binary multiplier calculator is used to perform the binary multiplication of 2 binary number formats very quickly and easily without using manual methods. Here is a question for you, what is an ASM chart?