Complex Programmable Logic Device (CPLD) Architecture and Its Applications

The designing process of digital hardware has transformed intensely over the past few years. So, small digital circuits can be implemented by using PALs and PLAs. Each device is used to implement various circuits that do not need more than the number of i/ps, o/ps and product terms that are offered in the specific chip. These chips are inadequate to fairly modest sizes, normally supporting a mutual number of inputs and outputs of not more than 32. For designing of these circuits that need more inputs and outputs, either numerous PLAs/ PALs can be employed or else a more classy type of chip can be used called a CPLD (complex programmable logic device). A CPLD chip includes several circuit blocks on a single chip with inside wiring resources to attach the circuit blocks. Each circuit block is comparable to a PLA or a PAL.

What is a Complex Programmable Logic Device?

The acronym of the CPLD is “Complex programmable logic devices”, it is a one kind of integrated circuit that application designers design to implement digital hardware like mobile phones. These can handle knowingly higher designs than SPLDs (simple programmable logic devices), but offer less logic than FPGAs (field programmable gate arrays).CPLDs include numerous logic blocks; each of the blocks includes 8-16 macrocells. Because every logic block executes a specific function, all of the macrocells in a logic block are fully connected. Depending upon the use, these blocks may or may not be connected to one another.

Complex Programmable Logic Device
Complex Programmable Logic Device

Most CPLDs (complex programmable logic devices) have macrocells with a sum of logic function and an elective FF (flip-flop). Depending on the chip, the combinatorial logic function supports from 4 to 16 product terms with inclusive fan-in. CPLDs also differ in terms of shift registers and logic gates. Due to this reason, CPLDs with a huge number of logic gates may be used instead of FPGAs. Another CPLD specification signifies the number of product terms that a macrocell can accomplish. Product terms are the product of digital signals that execute a specific logic function.

CPLDs are available in several IC package forms and logic families. CPLDs also differ in terms of supply voltage, operating current, standby current and power dissipation. In addition, these are obtainable with various amounts of memory and various kinds of memory support. Usually, memory is expressed in bits/ megabits. Memory support consists of ROM, RAM and dual-port RAM. It also comprises of CAM (content addressable memory) as well as FIFO (first-in, first-out) memory and LIFO (last-in, last-out) memory.

Architecture of Complex Programmable Logic Device

A complex programmable logic device comprises of a group of programmable FBs (functional blocks). The inputs and outputs of these functional blocks are connected together by a GIM (global interconnection matrix). This interconnection matrix is reconfigurable, so that we can modify the contacts between the functional blocks. There will be some input and output blocks that let us to unite CPLD to external world. The architecture of CPLD is shown below.

Generally, the programmable FB looks like the array of logic gates, where an array of AND gates can be programmed and OR gates are stable. But, each manufacturer has their way of thinking to design the functional block. A listed o/p can be found by operating the feedback signals attained from the OR gate outputs.

CPLD Architecture
CPLD Architecture

In CPLD programming, the design is first coded in Verilog or VHDL language once the code is (simulated and synthesized. During synthesis, the CPLD model (target device) is handpicked and a technology based mapping net list is produced. This list can be close-fitting to the genuine CPLD architecture using a place and route process, typically achieved by the place-and-route software of CPLD Company’s proprietary. Then the operator will do some confirmation processes. If everything is good, he will utilize the CPLD, else he will rearrange it.

Architecture Issues of CPLD

When considering a complex programmable logic device for use in design, there is some following architecture issues can be taken into account

  • The programming technology
  • The function block capability
  • The I/O capability

Some of the families of CPLD from different retailers include

  • Altera MAX 7000 and MAX 9000 families
  • Atmel ATF and ATV families
  • Lattice isp LSI family
  • Lattice (Vantis) MACH family
  • Xilinx XC9500 family
Families of CPLD
Families of CPLD

Applications of CPLD

The applications of CPLDs include the following

  • Complex programmable logic devices are ideal for high performance, critical control applications.
  • CPLD can be used in digital designs to perform the functions of boot loader
  • CPLD is used for loading the configuration data of a field programmable gate array from non-volatile memory.
  • Generally, these are used in small design applications like address decoding
  • CPLDs are frequently used many applications like in cost sensitive, battery operated portable devices due to its low size and usage of low power.

Thus, this is all about complex programmable logic device architecture and its applications. We hope that you have got a better understanding of this concept. Furthermore, any queries regarding this concept or to implement any electrical and electronic projects, please give your valuable suggestions by commenting in the comment section below. Here is a question for you, what is the difference between CPLD and FPGA?

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