What is PIPO Shift Register : Working, Truth Table, Circuit Diagram & Its Applications

A shift register is one type of sequential logic circuit where its output mainly depends on its input & previous output. This register includes a set of Flip Flops where these are connected within cascade which means, one FF output is simply connected to the input of another FF. This register is used to store as well as shift the group of binary data. The number of FFs available within the shift register mainly depends on the no. of binary bits stored within the register. For instance; if we want to store 2-bit binary data, then two flip-flops are required. So, this article discusses an overview of one of the types of shift register namely the PIPO shift register which is also called parallel in the parallel-out shift register.

What is PIPO Shift Register?

The shift register which uses parallel input and generates parallel output is known as the parallel input parallel output shift register. This shift register includes three connections only the PI (parallel i/p), PO (parallel o/p) & the CLK signal. This kind of shift register also works like a time delay device or temporary storage device like a SISO shift register with the time delay being changed through the CLK signals frequency.

In this type of register, the data is available in parallel format with respect to  the parallel i/p pins like PA to PD & after that, it is transferred directly together to their respective o/p pins from QA to QDby the similar CLK signal. After that single CLK signal will load & unload the shift register.

PIPO Shift Register Circuit Diagram

The circuit diagram of the PIPO shift register is shown below. The input allowed by this type of shift register is parallel & gives a parallel output. This logic circuit is designed with 4 D-FFs which is shown in the diagram. In this circuit, both the CLR and CLK signals are connected to 4 D FFs.

PIPO Shift Register Circuit Diagram
PIPO Shift Register Circuit Diagram

In this kind of shift register, there is no interconnection between the individual FFs because no serial data shifting is necessary. For each FF, the data is provided as i/p and the o/p is received from every FF individually.

How Does PIPO Shift Register Work?

This register is simply utilized like a temporary storage device similar to the SISO Shift register, so it works like a delay element. Here, the data which is given is in a parallel format to the parallel i/p pins like DA to D0 and after that shifted to the equivalent o/p pins from QA to QD once the shift registers are clocked. One CLK pulse is enough to load and one CLK pulse is to unload to the temporary storage device.

The design of this shift register is shown above which includes four inputs represented with DA, DB, DC & DD whereas corresponding FFs outputs are represented with QA, QB, QC & QD. Here, all the D FFs are connected in the same CLK pulse.

Now if we take the data input is 1101 which is loaded in each flip flop, initially, the output will become 0000. If we apply the first CLK pulse ‘1’ then the input data will be shifted from input DA to QA, so the output will become 1101.

Truth Table

The truth table of the PIPO shift register is shown below.




0 0 0 0
1 1 1 0


Timing Diagram

The PIPO shift register timing diagram is shown below. Here we are using positive edge clock input. If we use a positive edge CLK pulse, at that time the transition can take place. So the input data is to be shifted to output, so QA is ‘1’, QB is ‘1’, QC is ‘0’ and QD is ‘0’. This is the output data.

Timing Diagram
Timing Diagram

PIPO Shift Register Verilog Code

The verilog code for PIPO shift register is shown below.

module pipo(din,clk,rst,dout);
input [3:0] din;
input clk,rst;
output [3:0] dout;wire [3:0] din;
wire clk,rst;
reg [3:0] dout;
always @(posedge clk or negedge rst)
dout <= 4’b0;
begindout <= din;

Advantages and Disadvantages

The advantages of the PIPO shift register include the following.

  • These shift registers are very easy and fast to utilize.
  • They work very fast as compared to logic circuits while converting data.
  • The Sequence number of Pseudo Noise within CDMA is generated through them.
  • It occupies less space and decreases the usage of wiring.
  • Data conversion is easy in shift registers.
  • Its design is very simple.
  • Data encryption & decryption is possible by using shift registers.
  • Data tracking is also possible by using them.

The main disadvantage of this shift register is, that the output current strength received from this register is not very strong.


The applications of the PIPO shift register include the following.

  • The PIPO shift register is mainly used to add time delay to digital circuits.
  • Shift registers are used for converting data and also to shift the data from left to right and right to left.
  • It is used for storing the data.
  • These types of shift registers are also used for data storage, manipulation & data transfer.
  • This is a temporary storage device where both data loading & retrieval processes take place within the parallel mode.

Thus, this is an overview of parallel in parallel-out shift register – working with applications. In this shift register, the parallel i/p data is given to the FF to get the parallel output. Here, the output mainly depends on the input applied in a similar CLK cycle. This type of shift register doesn’t include any connection between individual D flip-flops. As compared to other types of shift registers, the D FFs in this shift register use similar CLK for loading & unloading data. The most frequently used PIPO shift register ICs are; 4-bit bidirectional 40104 IC, 7495 IC 4-bit shift register and 5-bit 7496 IC PIPO shift register. Here is a question for you, what is the SISO shift register?

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