What is SISO Shift Register : Working, Truth table, Circuit diagram & Its Applications
Generally, a Flip Flop is used to store one data bit. If we want to store multiple data buts, we require a number of flip-flops. So, the set of flip-flops is called a register which is used to shift the bits. There are different kinds of registers available based on inputs applied and outputs accessed like SISO, SIPO, PISO, and PIPO. If the register is used to shift the bits either on the right side or left side then it is called a shift register. This article discusses one of the types of shift register namely the SISO register or serial in and serial-out shift register.
What is SISO Shift Register?
The term “SISO” stands for “Serial-In Serial-Out”. The SISO shift register circuit accepts serial data on its input pin and shifts it out serially on its output pin. The number of bits that can be shifted out before the next bit arrives depends on the speed of the clock signal that controls the operation of the shift register. This type of shift register can be used as a buffer between two asynchronous devices that communicate with each other using signals with different frequencies or phases.
The SISO shift register block diagram is shown below which includes 3-D flip-flops. The connection of these FFs can be done by connecting the one Flip Flops output to the next flip flop input. So these FFs are synchronous through each other because the equal CLK signal is applied in each Flip Flop.
This shift register includes simply three connections the SI (serial input), SO (serial output), and CLK (clock signal). Here, the SI determines the input enters into the left-hand side flip-flop, the SO is the output taken from the right-hand side flip-flop & the sequencing CLK signal.
In this type of shift register, the bits can be transmitted serially from the serial input of the flip flop. For each clock signal in the FFs, the data can be transmitted from one phase to the next phase. As a result, we can get the bits in sequence from the D-FFs output which is known as serial output.
SISO Shift Register Circuit Diagram
We know that the input in this type of shift register is serially fed whereas the output is received in a serial way. The SISO shift register circuit diagram is shown below where the D FFs like D0 to D3 are connected serially as shown in the following diagram.
At first, all the four D flip-flops are set to reset mode so that each flip-flop’s output within the circuit is low which is ‘0’.
This is a shift right mode circuit which means when the data i/p is given at the left end of the flip flop then the stored bit can be shifted to the right side to generate serial output. Now let us discuss how the given data is stored within this register.
Working of SISO Shift Register
Let us take an example of the 1011 binary number. Before that, the circuit must be set to reset mode so the output of every register will be ‘0’, so the output provided by all the registers will be “0000”.
In this 4-bit shift register example like “1111”, the LSB bit is ‘1’ and the MSB bit is ‘1’. First, the high signal (LSB bit) is used as an input to the first D3 flip flop, then D3=1. But primarily all the D FFs outputs will be 0. So, D2=D1=D0=0. When D3 input is high signal (1) then D3 will cause ‘Q3’ to be ‘1’. Therefore the overall o/p for 1st falling edge will become 1000.
Similarly, when the next data i/p bit in the above 4-bit like high signal (1) is given at flip flop D3, again this ‘D3’ will cause ‘Q3’ to be 1, however, ‘Q3’ is given as input to FF ‘D2’. So, this ‘D2’will cause ‘Q2’ to be 1 when all the remaining outputs will become 0.
As a result, we will obtain ‘11’ for a 2nd falling edge; so will obtain ‘11’ at the stored bit in the shift register, thus the overall o/p for the 2nd falling edge will get o/p as“1100”.
When the third input bit like high signal (1) is applied at the ‘D3’ FF then earlier ‘Q2’ o/p will cause the ‘D1’ i/p to be ‘0’. This will give the output Q3, Q2 & Q1 as ‘1’ whereas ‘Q0’ will be ‘0’. So the overall o/p for the 3rd falling edge will get o/p as “1110”.
In addition, an MSB bit like high signal (1) is given as input, after that ‘1’ at ‘Q1’ will cause input ‘D0’ to be ‘1’, thus, this will make ‘Q0’ be ‘1’. Therefore, finally, SISO shift register store 1111 bit & shows in the o/p.
The SISO shift register truth table is shown below.
CLK |
‘Q3’ | ‘Q2’ | ‘Q1’ |
‘Q0’ |
Initially (Reset) |
0 |
0 | 0 | 0 |
1^{st} Falling Edge |
1 | 0 | 0 | 0 |
2^{nd} Falling Edge |
1 | 1 | 0 |
0 |
3^{rd} Falling Edge | 1 | 1 | 1 |
0 |
4^{th} Falling Edge | 1 | 1 | 1 |
1 |
By considering the above truth table, the SISO shift register waveform representation will be like the following.
In the above waveform, the 1st waveform is the CLK i/p signal whereas the 2nd waveform shows the data i/p to be stored as ‘1111’. So the waveform will be a constant high signal. In addition, the above-shown waveform will represent the 4 data o/p of the FFs.
Firstly, all the FFs o/ps were ‘0’ which is very clearly given in the above representation of the waveform. But, the ‘Q3’ output will vary from ‘0’ to ‘1’ once the 1st CLK signal arrives while the remaining o/ps are still ‘0’.
In this way, the 2nd CLK signal ‘Q2’ will vary from ‘0’ to ‘1’. As a result, both ‘Q2’ & ‘Q3’ will show logic high within the above waveform.
That how a SISO shift register operates. Once the 4th CLK signal arrives then all the four registers outputs will become ‘1’. So the storage can be performed by shifting each bit on the arrival of every CLK signal so it is called a SISO shift register.
Verilog Code
The verilog code for SISO shift register is shown below.
module sisomod(clk,clear,si,so);
input clk,si,clear;
output so;
reg so;
reg [3:0] tmp;
always @(posedge clk )
begin
if (clear)
tmp <= 4’b0000;
else
tmp <= tmp << 1;
tmp[0] <= si;
so = tmp[3];
end
endmodule
Applications
The SISO shift register applications include the following.
- The SISO shift register is mainly used to generate time delays in digital logic circuits.
- These shift registers are used to transfer manipulation and store the data.
- SISO register is used efficiently to decrease the no. of wires connecting the different systems within the design.
- SISO shift register delays data through a single CLK time for every stage & they will store a data bit for every register.
- These types of registers are mainly used especially for time delays.
Thus, this is all about an overview of the SISO shift register – working with applications. Similarly, the SISO shift register using Jk Flip-Flop can also be designed like using D flip flops but it needs the connection of both the inputs of J & K. Like the above D-FF-based shift register, in the JK FF-based shift register also both the inputs are given at the left side flip flop where all the FFs are serially connected. Here is a question for you, what is a Bidirectional shift register?