# PISO Shift Register : Working, Circuit ,Timing diagram, Verilog code & Its Applications

We know that a Flip flop is used to store a single binary data bit but if we want to store multiple data bits then several FFs are required. So a shift register includes a set of FFs used for storing multiple data bits by connecting them serially. The data which is stored in these registers can be shifted by using CLK signals. The shift registers which are used for shifting the data bits to left are known as SLR or Shift left register whereas the data bits that are shifted to the right side are known as SRR or Shift right register. We know that these registers are classified into different types like SISO, SIPO, PISO, and PIPO. So this article discusses an overview of a PISO shift register which is known as a parallel in the serial-out shift register.

## What is PISO Shift Register?

The shift register which uses parallel input and generates serial output is known as the parallel input serial output shift register or PISO shift register. This shift register works in a reverse way to the SIPO shift register. In this type of shift register, the input data enters a parallel way and comes out serially. So the i/p of the second FF is the o/p of the first flip flop.

### PISO Shift Register Circuit Diagram

The PISO shift register circuit diagram is shown below. This circuit mainly includes 4 D FFs which are connected as per the diagram shown. The CLK i/p signal is connected directly to all the FFs however the i/p data is individually connected to every flip flop.

The previous FF’s o/p, as well as parallel input data, is simply connected to the i/p of the second flip flop. So the FFs in the circuit are synchronous through each other because a similar CLK signal is given to every flip flop.

#### PISO Shift Register Working

In the above-shown PISO shift register circuit, the input data is applied to the input pins of the shift registers from DA to DD  at the same time. After that, it is read out from the shift register serially 1-bit at a time from input pins on every CLK cycle. Here, one CLK pulse is enough to load the 4-bit of data but four pulses are required to unload all the four bits.

In this parallel input serial output (PISO) shift register circuit, logic gates are used.  One control signal (Shift/Load) is used to control the parallel input and serial output. After that, NOT gate outputs are connected to ‘G1’, ‘G2’, and ‘G3’, and the other inputs of G1, G2 & G3 are B, C & D. Here, ‘A’ is directly connected to DA of the first flip flop.

The direct control signal is connected to one input of the ‘G4’, ‘G5’ & ‘G6’ and one more input of the ‘G4’, ‘G5’ & ‘G6’ are connected to the outputs of Flip Flops like QA, QB, and QC. The OR gate is connected to the second, third, and fourth Flip Flop’s inputs like DB, DC, and DD. All the flip flops are to be connected in a single CLK pulse and the FFs outputs will be in the serial data output.

Now we are going to see how the data is loaded. Here, we are choosing the input data as 1101 then A=1, B=1, C=0 & D=1. When the control signal applied to NOT gate is ‘0’ then its o/p will become‘1’ and ‘G1, ‘G2’ & ‘G3’ will enable, and ‘G4’, ‘G5’ & ‘G6’ will disable. So all the inputs are loaded and after that OR gates are also enabled and the data is to be loaded to the input of each Flip Flop.

Now we are applying the control signal ‘1 to NOT gate then the output of this gate will become ‘0’ then G4, G5 & G6 are enabled. Once the CLK pulse is applied to FFs, then the data ‘1101’ is shifted to the right side from one OR gate to the other.

### The PISO shift register truth table is shown below.

Now the control signal applied is ‘0’ then the data to be loaded and the data will become 1101.

 DA DB DC DD 1 1 0 1

Now the control signal applied is ‘1’ and the CLK pulse ‘1’ is applied then the data is shifted like QA becomes ‘1’, QB becomes ‘1’, QC becomes ‘0’ and QD becomes ‘1’ as shown in the following table.

 CLK Pulse QA QB Qc QD (Data Output) 0 0 0 0 0 1 1 1 0 1 2 0 1 1 0 3 0 0 1 1 4 0 0 0 1

If the CLK pulse ‘2’ is applied then the data is shifted like QA becomes ‘0’, QB becomes ‘1’, QC becomes ‘1’ and QD becomes ‘0’ as shown in the following table.

If the CLK pulse ‘3’ is applied then the data is shifted like QA becomes ‘0’, QB becomes ‘0’, QC becomes ‘1’ and QD becomes ‘1’ as shown in the following table.

If the CLK pulse ‘4’ is applied then the data is shifted like QA becomes ‘0’, QB becomes ‘0’, QC becomes ‘0’ and QD becomes ‘1’ as shown in the following table.

#### PISO Shift Register Timing Diagram

The timing diagram of the PISO shift register is shown below. Here we are using a positive edge CLK i/p signal. Once the CLK pulse is applied then all the data is to be shifted from QA, QB, QC & QD. After the second CLK pulse, the ‘1’ is moving to the third and fourth CLK pulses which are shown in the diagram. So the final data output after the fourth CLK will be 1011.

### Verilog Code

The verilog code for PISO shift register is shown below.

input [3:0]Parallel_In;
output reg Serial_Out;
reg [3:0]tmp;
always @(posedge Clk)
begin
tmp<=Parallel_In;
else
begin
Serial_Out<=tmp;
tmp<={tmp[2:0],1’b0};
end
end
endmodule

### Applications

The applications of the PISO shift register include the following.

• A PISO shift register is used to change the data from parallel to serial form.
• This kind of shift register is used to generate time delay for digital circuits.
• PISO shift register’s practical application is to read numerous switch closures into a chip on a few pins.
• This register reads the data into a memory chip.

Thus, this is an overview of the PISO shift register – working and its applications. The most frequently used PISO shift register ICs are; 74HC165 IC, 74HC164 IC, 74674 IC & 74HC595 IC. Here is a question for you, what is the SISO shift register?