# Circuit Designing of Sample and Hold Circuit using Op-Amp

In electronics, a sample and hold (S&H) circuit is an analog device that is used to take the voltage of a constantly changing analog signal and locks its value at a stable level for a particular least period of time. These circuits are the basic analog memory devices. They are normally used in ADC (analog-to-digital converters) to get rid of differences in the input signal that can damage the change process. A typical circuit of the sample and hold stores electric charge in a capacitor and holds at least one switching device like a field effect transistor switch and usually one op-amp (operational amplifier).

To sample the i/p signal the switch unites the capacitor to the o/p of a buffer amplifier. This amplifier amplifies the capacitor so that the voltage across the capacitor is almost equal, or proportional to input voltage. In hold form, the switch separates the capacitor from the buffer. The capacitor is always discharged by its own outflow currents and helpful load currents, which makes the circuit essentially unstable, but the voltage drop in a particular hold time remains within a suitable error margin.

## What is Sample and Hold Circuit?

The sample & hold circuit is an electronic circuit which makes the examples of voltage given to it as information, and from that point onward, it holds these samples for the positive time. The time amid which sample and hold circuit produces the sample of i/p signal is called sampling time. Correspondingly, the time length of the circuit amid which it holds the sampled value is called holding time.

Generally, the sampling time is between 1µs-14 µs while the holding time can expect any value as necessary in the application. It will not be wrong to state that capacitor is the core of sample and hold circuit. This is because the capacitor exhibit in it charges to its peak value when the switch is opened, i.e. during sampling and holds the inspected voltage when the switch is shut.

### Sample and Hold Circuit Diagram

The below circuit diagram shows the sample and hold circuit with the help of an Op-Amp. It is plain from the circuit diagram that two op-amps are linked through a switch. When the switch is locked sampling method will come into the image and when the switch is unlocked holding outcome will be there. The capacitor allied to the second op-amp is nothing but a holding capacitor.

By using this sample and hold circuit we can get samples of the analog signal, followed by a capacitor. It holds these samples for a particular time. As a result of this, a stable signal is produced this can be changed into the digital signal with the help of ADC (analog to digital converters).

### Sample and Hold Circuit Working

The working of this circuit can be simply understood using its components working. The main components to build the sample and hold circuit include an N-channel Enhancement type MOSFET, a capacitor, and a high accuracy operational amplifier.

As a switching element, the N-channel Enhancement MOSFET is used. The input voltage is given via its drain terminal and control voltage is also given through its gate terminal. When the +ve pulse of the control voltage is applied, the MOSFET will be activated state. And it performs as a closed switch. On the opposing, when the control voltage is nothing then the MOSFET will be deactivated state and works as the open switch.

When the MOSFET works as a closed switch, the analog signal given to it through the drain terminal will be fed to the capacitor. Then the capacitor will charge to its peak value. When the switch is released, then the capacitor discontinues charging. Due to the high impedance op-amp connected at the circuit end, the capacitor will knowledge high impedance due to this it cannot get discharged

This directs to the holding of the charge by the capacitor for the exact amount of time. This can be referred as holding period. And the time in which samples of i/p voltage is produced is named sampling period. The o/p processed by op-amp throughout the holding period. So, holding period holds implication for Op-Amps.

#### Input & Output Waveforms

The waveforms of the sample and hold circuit as explained in the following diagram. It is clear from the waveform of the circuit, that during the ON period what will be the voltage at the o/p. Throughout the OFF period the voltage that exists at the o/p of the op-amp.

#### Sample and Hold Circuit Applications

The applications of sample and hold circuit include the following

• Sampling Oscilloscopes
• Data Distribution System
• Digital Voltmeters
• Analog Signal Processing
• Signal Constructional Filters
• Data Conversion System

Thus, this is all about the sample and hold circuit. In simple terms, this circuit produces the samples of the analog i/p signal and holds the most recent sampled values for exact time and replicates it at the o/p. We hope that you have got a better understanding of this concept. Furthermore, any queries regarding this concept or to implement any electrical projects please give your feedback by commenting in the comment section below. Here is a question for you, what is the function of sample and hold circuit?