Introduction to Counters – Types of Counters

Counter is a digital device and the output of the counter includes a predefined state based on the clock pulse applications. The output of the counter can be used to count the number of pulses. Generally, counters consist of a flip-flop arrangement which can be synchronous counter or asynchronous counter. In synchronous counter, only one clock i/p is given to all flip-flops, whereas in asynchronous counter, the o/p of the flip flop is the clock signal from the nearby one. The applications of the microcontroller need counting of exterior events such as exact internal time delay generation and the frequency of the pulse trains. These events are frequently used in digital systems & computers. Both these events can be executed by software techniques, but software loops for counting will not give the exact result slightly more important functions are not done. These problems can be rectified by timers and counters in the microcontrollers which are used as interrupts.

Counters
Counters

Types of Counters

Counters can be categorized into different types according to the way they are clocked. They are


  • Asynchronous Counters
  • Synchronous Counters
  • Asynchronous Decade Counters
  • Synchronous Decade Counters
  • Asynchronous Up-Down Counters
  • Synchronous Up-Down Counters

For better understanding of this type of counters, here we are discussing some of the counters.

Asynchronous Counters

The diagram of a 2-bit asynchronous counter is shown below. The exterior clock is connected to the clock i/p of the FF0 (first flip-flop) only. So, this FF changes the state at the decreasing edge of every clock pulse, but FF1 changes only when activated by the decreasing edge of the Q o/p of FF0. Because of the integral propagation delay through a FF, the change of the i/p clock pulse and a change of the Q o/p of FF0 can never occur at precisely the same time. So, the FF’s cannot be activated concurrently, generating an asynchronous operation.

Asynchronous Counters
Asynchronous Counters

Note that for ease, the changes of Q0,Q1 & CLK in the above diagram are shown as concurrent, even though this is an asynchronous counter. Actually, there is a small delay b/n the Q0, Q1 and CLK changes.

Generally, all the CLEAR i/ps are connected together, so before counting starts then that a single pulse can clear all the FFs. The clock pulse fed into FF0 is rippled through the new counters after propagation delays, such as a ripple on the water, hence the term Ripple Counter.

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The circuit diagram of the two bit ripple counter includes four different states ,each one consisting with a count value. Likewise, a counter with n FFs can have 2N states. The number of states in a counter is called as its mod number. Therefore a two-bit counter is a mod-4 counter.

Asynchronous Decade Counters

In the previous counter have 2n states. But, counters with states less than 2n is also possible. These are designed to have the no. of states in their series.These are called shortened sequences which are accomplished by driving the counter to recycle before going through all of its states. A common modulus for counters with shortened sequence is 10. A counter with 10-states in its series is called a decade counter.The implemented decade counter circuit is given below.

Asynchronous Decade Counter Circuit Diagram
Asynchronous Decade Counter Circuit Diagram

When the counter counts to ten, then all the FFs will be cleared. Notice that only Q1&Q3 both are used to decode the count of 10, that is called partial decoding. At the same time one of the other states from 0-9 have both Q1&Q3 will be high. The series of the decade counter table is given below.

Sequence of the Decade Counter
Sequence of the Decade Counter

Asynchronous Up-Down Counters

In particular applications, a counter must be capable to count both up & down. The below circuit is a three bit up & down counter, that counts UP or DOWN based on the control signal status. When the UP i/p is at 1 & the DOWN i/p is at 0, the NAND gate between FF0 & FF1 will gate the non-inverted o/p (Q) of flip flop (FF0) into the clock i/p of flip flop (FF1). Likewise, the non-inverted o/p of Flip Flop1 will be gated through the other NAND gate into the clock i/p of flip-flop2. Therefore the counter will count up.

Asynchronous Up-Down Counter Circuit Diagram
Asynchronous Up-Down Counter Circuit Diagram

Once the control i/p (UP) is at 0 & DOWN is at 1, the inverted o/ps of flip-flop0 (FF0) and flip-flop1 (FF) are gated into the clock i/ps of FF1 & FF2 separately. If the FFs are initially changed to 0’s, then the counter will go through the below series as i/p pulses are applied. Notice that an asynchronous up-down counter is slower than an UP counter/down counter because of an extra propagation delay introduced by the NAND gates.

Sequence of the Asynchronous Up-Down Counter
Sequence of the Asynchronous Up-Down Counter

Synchronous Counters

In this type of counters, the CLK i/ps of all the FFs are connected together and are activated by the i/p pulses. So, all the FFs change states instantaneously. The circuit diagram below is a three bit synchronous counter. The inputs J and K of flip-flop0 are connected to HIGH. Flip-flop 1 has its J &K i/ps connected to the o/p of flip-flop0 (FF0), and the inputs J & K of flip-flop2 (FF2) are connected to the o/p of an AND gate that is fed by the o/ps of flip-flop0 and flip-flop1. When the both the outputs of FF0 & FF1 are HIGH. The positive edge of the fourth CLK pulse will cause FF2 to alter its state because of the AND gate.

Synchronous Counter Circuit Diagram
Synchronous Counter Circuit Diagram

The series of the three bit counter table is given below.The major advantage of these counters is that there is no increasing time delay due to all FFs are activated in parallel. Thus, the max operating frequency of this synchronous counter will be considerably higher than for the equivalent ripple counter.

CLK Pulses of the Synchronous Counters
CLK Pulses of the Synchronous Counters

Synchronous Decade Counters

Synchronous counter counts from 0-9 similar to asynchronous counter and then again recycles zero. This process is done by driving the 1010 states back to the 0000 state. This is termed as truncated sequence, that can be designed by the below circuit.

Synchronous Decade Counter Circuit Diagram
Synchronous Decade Counter Circuit Diagram

From the series on the left table, we can observe that

  • Q0 ties on each and every CLK pulse
  • Q1 alters on the next clock pulse every time when Q0=1 & Q3=0.
  • Q2 alters on the next clock pulse every time when Q0=Q1=1.
  • Q3 alters on the next CLK pulse each and every time when Q0=1, Q1=1 & Q2=1 (count 7), or when Q0=1 & Q3=1 (count 9).
Sequence of the Synchronous Decade Counter
Sequence of the Synchronous Decade Counter

The above characteristics are employed with the AND gate or OR gate. The logic diagram of this is shown in the above diagram.

Synchronous Up-Down Counters

A three bit synchronous Up-Down counter, tabular form and series are given below. This type of counter has an up-down control i/p similar to asynchronous up-down counter, that is used to control the counter’s direction through a certain series.

Synchronous Up-Down Counters Circuit Diagram
Synchronous Up-Down Counters Circuit Diagram

The series of the table shows

  • Q0 ties on each CLK pulse for both up & down series
  • When Q0=1 for the up series, then the state of the Q1 changes on the next CLK pulse.
  • When Q0=0 for the down series, then the state of the Q1 changes on the next CLK pulse.
  • When Q0=Q1=1 for the up series, then the state of the Q2 changes on the next CLK pulse.
  • When Q0=Q1=0 for the down series, then the state of the Q2 changes on the next CLK pulse.
Sequence of the Synchronous Decade Counters
Sequence of the Synchronous Decade Counters

The above characteristics are employed with the AND gate, OR gate and NOT gate. The logic diagram of this is shown in the above diagram.

Applications of Counters

The applications of the counters mainly involve in digital clocks and in multiplexing. The best example of the counter is parallel to serial data conversion logic discussed below.

A set of bits, performing concurrently on parallel lines is called parallel data. A set of bits, performing on a single line in a time series is called serial data. The Parallel-to-serial data conversion is normally is done by using a counter to afford a binary series of the data, select i/ps of a MUX, as explained in the circuit below.

Parallel-to-Serial Data Conversion
Parallel-to-Serial Data Conversion

In the above circuit, modulo-8 counter consist of Q o/ps, that are connected to the data, select i/ps of an 8-bit MUX. The first 8-bit group of parallel data is applied to the inputs of the MUX. As the counter goes through a binary series from 0-7, each bit starts with D0, is serially selected & passed through the MUX to the o/p line. After 8-CLK pulses, the data byte has been changed to a serial format & sent out through the transmission line. Then, the counter reprocesses back to 0 and changes another parallel byte serially again in the similar process.

Thus, this is all about the counters and types of counter, which includes Asynchronous Counters, Synchronous Counters, Asynchronous Decade Counters, Synchronous Decade Counters, Asynchronous Up-Down Counters and Synchronous Up-Down Counters. Furthermore, any doubts regarding this topic or timers and counters in 8051 microcontroller please comment in the comment section below.

2 Comments

  1. Shivani Dahiya says:

    Very helpful and useful . Thank you very much .

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