74LS138 IC: Pin Diagram, Circuit and Applications

The decoder 74LS138 IC uses advanced technology like silicon (Si) gate TTL technology. These are suitable for different applications like memory address decoding otherwise data routing. These applications will feature high-noise resistance & low power utilization typically allied with TTL circuitry. This 74LS138 IC has 3-binary select inputs like A, B, & C. If the IC is activated, then these input pins will decide which of the 8 usually HIGH o/ps will go LOW. The enable pins are two active low & one active high. The output of the decoder can drive 10 low-power Schottky TTL equal loads, and all the inputs are defended from harm because of static discharge with diodes toward VCC as well as the ground. This article discusses an overview of 74LS138 IC:3 to 8 Line Decoder IC.

What is a 74LS138 IC?

The IC 74LS138 is a 3 to 8 line decoder integrated circuit from the 74xx family of transistor-transistor-logic-gates. The main function of this IC is to decode otherwise demultiplex the applications. The setup of this IC is accessible with 3-inputs to 8-output setup. This IC is mainly used in applications like memory decoding with high performance otherwise data routing, etc. These ICs can be used for minimizing the system decoding effects in memory systems with high performance. This IC includes three enable pins (where two pins are active low and one is active high) decreases the necessity of outside gates. The implementation of 24 line decoder can be done without using outside inverters, as well as a 32-line decoder needs a single inverter

This IC is mainly used in de-multiplexing applications with the help of an enable pin like a data input pin. And also the inputs of this IC is clamped with Schottky diodes which are the high performance to contain line ringing as well as system design simplify.

74LS138 Pin Configuration

The IC 74LS138 is a 16-pin integrated circuit, and each pin of this IC is discussed below. The similar 74LS138 IC’s are

74LS138 Pin Configuration
74LS138 Pin Configuration
  • Pin1 (A): Address input pin
  • Pin2 (B): Address input pin
  • Pin3 (C): Address input pin
  • Pin4 (G2A): Active low enable pin
  • Pin5 (G2B): Active low enable pin
  • Pin6 (G1): Active high enable pin
  • Pin7 (Y7): Output pin
  • Pin8 (GND): Ground pin
  • Pin9 (Y6): Output pin 6
  • Pin10 (Y5): Output pin 5
  • Pin11 (Y4): Output pin 4
  • Pin12 (Y3): Output pin 3
  • Pin13 (Y2): Output pin 2
  • Pin14 (Y1): Output pin 1
  • Pin15 (Y0): Output pin 0
  • Pin16 (VCC): Power supply pin

74LS138 IC Features

The features of the 74LS138 IC include the following.

  • This IC is particularly designed for high-speed
  • Decoding capacity
  • Integrates 3-enable pins for simplifying cascading
  • Security of ESD
  • Impartial propagation delays
  • Supply voltage ranges from 1.0V-5.5V
  • Inputs allow voltages superior to VCC
  • Standard propagation delay is 21nS
  • Power consumption is low-32mW
  • Schottky clamped for high-performance
  • Operating temperature is from -40ºC to +125ºC

How to Use the 74LS138 IC?

To understand the IC working, let us design a simple circuit with few required basic electronic components as shown below. In the above circuit, the outputs are allied toward light emitting diode to illustrate which o/p-pin goes LOW & outputs of the IC are inverted.


Here we have used a single device so the connections of G2A, as well as G2B pins, are connected to GND followed by linking G1-to-VCC for activating the chip.

74LS138 IC Table
74LS138 IC Table

Here three buttons signify three i/p lines for this device. For a better understanding of this concept, let us understand the following truth table. In the above tabular form, the H-HIGH, L-LOW and X- don’t care. The enable pins G1, G2A, and G2B, where G2=G2A + G2B.

In the above tabular form, the first rows namely G1, G2 are the enable pins required to be connected correctly otherwise irrespective of all i/p, as well as o/p lines, will be high. Once the enable pins are connected, then the input line can be connected for getting the output.

74LS138 IC Logic Diagram
74LS138 IC Logic Diagram

After connecting, if all switches are not pushed Y0 will be LOW & residual o/p will be HIGH shown in the above tabular form. When B1 is pushed, A0 will be HIGH & Y1 will become LOW whereas remaining will be HIGH. When B2 is only pressed, A1 will be HIGH & Y2 will become LOW whereas remaining will be HIGH. In this way, we can understand the entire truth table with toggling the three switches namely B1, B2 & B3, and the inputs are A0, A1 & A2.

Applications of 74LS138 IC

The applications of IC 74LS138 include the following.

  • Line decoders
  • Memory circuits
  • Servers
  • Digital systems
  • Line De-multiplexing
  • Telecom circuits

Thus, this is all about 3 to 8 line decoder 74LS138 IC data sheet. As discussed previously, this IC is particularly designed to utilize within memory decoding with high performance otherwise in the routing of the data applications which need very little propagation delay times. The data exchange rate of memory unit decides the act of any application & the holdups of any type are not acceptable there. So, IC74LS138 line decoder is ideal in such applications. Because, the holdup times of this IC are fewer than the usual memory access time, which means the efficient system holdup introduced with the decoder is insignificant to have an effect on the performance.

Image Source: Texas Instruments