Understanding about RISC and CISC Architectures

Instruction set or instruction set architecture is the structure of the computer that provides commands to the computer to guide the computer for processing data manipulation. Instruction set consists of instructions, addressing modes, native data types, registers, interrupt, exception handling and memory architecture. Instruction set can be emulated in software by using an interpreter or built into hardware of the processor. Instruction Set Architecture can be considered as a boundary between the software and hardware. Classification of microcontrollers and microprocessors can be done based on the RISC and CISC instruction set architecture.

Instruction set of Processor
Instruction set of Processor

Instruction set specifies processor functionality including the operations supported by the processor, storage mechanisms of the processor, and the way of compiling the programs to the processor.

What is RISC and CISC?

The RISC and CISC can be expanded as follows:

RISC represents the Reduced Instruction Set Computer and
CISC represents the Complex Instruction Set Computer.

RISC (Reduced Instruction Set Computer) Architecture

RISC Architecture
RISC Architecture

The microcontroller architecture that utilizes small and highly optimized set of instructions is termed as the Reduced Instruction Set Computer or simply called as RISC. It is also called as LOAD/STORE architecture.

In the late 1970s and early 1980s, RISC projects were primarily developed from Stanford, UC-Berkley and IBM. The John Coke of IBM research team developed RISC by reducing the number of instructions required for processing computations faster than the CISC. The RISC architecture is faster and the chips required for the manufacture of RISC architecture is also less expensive compared to the CISC architecture.


Typical Features of RISC Architecture

  • Pipelining technique of RISC, executes multiple parts or stages of instructions simultaneously such that every instruction on the CPU is optimized. Hence, the RISC processors have Clock per Instruction of one cycle, and this is called as One Cycle Execution.
  • It optimizes the usage of register with more number of registers in the RISC and more number of interactions within the memory can be prevented.
  • Simple addressing modes, even complex addressing can be done by using arithmetic AND/ OR logical operations.
  • It simplifies the compiler design by using identical general purpose registers which allows any register to be used in any context.
  • For efficient usage of the registers and optimization of the pipelining uses, reduced instruction set is required.
  • The number of bits used for the opcode is reduced.
  • In general there are 32 or more registers in the RISC.

Advantages of RISC processor architecture

  • Because of the small set of instructions of RISC, high-level language compilers can produce more efficient code.
  • RISC allows freedom of using the space on microprocessors because of its simplicity.
  • Instead of using Stack, many RISC processors use the registers for passing arguments and holding the local variables.
  • RISC functions uses only a few parameters, and the RISC processors cannot use the call instructions, and therefore, use a fixed length instructions which are easy to pipeline.
  • The speed of the operation can be maximized and the execution time can be minimized.
  • Very less number of instruction formats (less than four), a few number of instructions (around 150) and a few addressing modes (less than four) are needed.

Drawbacks of RISC processor architecture

  • With the increase in length of the instructions, the complexity increases for the RISC processors to execute due to its character cycle per instruction.
  • The performance of the RISC processors depends mostly on the compiler or programmer as the knowledge of the compiler plays a major role while converting the CISC code to a RISC code; hence, the quality of the generated code depends on the compiler.
  • While rescheduling the CISC code to a RISC code, termed as a code expansion, will increase the size. And, the quality of this code expansion will again depend on the compiler, and also on the machine’s instruction set.
  • The first level cache of the RISC processors is also a disadvantage of the RISC, in which these processors have large memory caches on the chip itself. For feeding the instructions, they require very fast memory systems.

CISC (Complex Instruction Set Computer) Architecture

The main intend of the CISC processor architecture is to complete task by using less number of assembly lines. For this purpose, the processor is built to execute a series of operations. Complex instruction is also termed as MULT, which operates memory banks of a computer directly without making the compiler to perform storing and loading functions.

CISC Architecture
CISC Architecture

Features of CISC Architecture

  • To simplify the computer architecture, CISC supports microprogramming.
  • CISC have more number of predefined instructions which makes high level languages easy to design and implement.
  • CISC consists of less number of registers and more number of addressing modes, generally 5 to 20.
  • CISC processor takes varying cycle time for execution of instructions – multi-clock cycles.
  • Because of the complex instruction set of the CISC, the pipelining technique is very difficult.
  • CISC consists of more number of instructions, generally from 100 to 250.
  • Special instructions are used very rarely.
  • Operands in memory are manipulated by instructions.

Advantages of CISC architecture

  • Each machine language instruction is grouped into a microcode instruction and executed accordingly, and then are stored inbuilt in the memory of the main processor, termed as microcode implementation.
  • As the microcode memory is faster than the main memory, the microcode instruction set can be implemented without considerable speed reduction over hard wired implementation.
  • Entire new instruction set can be handled by modifying the micro program design.
  • CISC, the number of instructions required to implement a program can be reduced by building rich instruction sets and can also be made to use slow main memory more efficiently.
  • Because of the superset of instructions that consists of all earlier instructions, this makes micro coding easy.

Drawbacks of CISC

  • The amount of clock time taken by different instructions will be different – due to this – the performance of the machine slows down.
  • The instruction set complexity and the chip hardware increases as every new version of the processor consists of a subset of earlier generations.
  • Only 20% of the existing instructions are used in a typical programming event, even though there are many specialized instructions in existence which are not even used frequently.
  • The conditional codes are set by the CISC instructions as a side effect of each instruction which takes time for this setting – and, as the subsequent instruction changes the condition code bits – so, the compiler has to examine the condition code bits before this happens.


  • The wasting cycles can be prevented by the programmer by removing the unnecessary code in the RISC, but, while using the CISC code leads to wasting cycles because of the inefficiency of the CISC.
  • In RISC, each instruction is intended to perform a small task such that, to perform a complex task, multiple small instruction are used together, whereas only few instructions are required to do the same task using CISC – as it is capable of performing complex task as the instructions are similar to a high-language code.
  • CISC is typically used for computers while RISC is used for smart phones, tablets and other electronic devices.

The following figure shows more differences between RISC and CISC


Thus, this article discusses about the RISC and CISC architectures; features of the RISC and CISC processors architecture; advantages and drawbacks of RISC and CISC, and differences between the RISC and CISC architectures with a brief idea. For more information regarding the RISC and CISC architectures, please post your queries by commenting below.

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