What is a Half Subtractor : Circuit using Logic Gates
In the domain of electronics, the most crucial concept that every component works on is the “Logic Gates“. As the concept of logic gates is implemented in every functionality such as in integrated circuits, sensors, switching purposes, microcontrollers and processors, encryption and decryption purposes, and others. In addition to these, there are wide applications of Logic Gates. There are many types of logic gates such as Adder, Subtractor, Full Adder, Full Subtractor, Half Subtractor, and many others. So, this article provides collective information of half subtractor circuit, half subtractor truth table, and related concepts.
What is Half Subtractor?
Before going to discuss the half subtractor, we have to know the binary subtraction. In binary subtraction, the process of subtraction is similar to arithmetic subtraction. In arithmetic subtraction the base 2 number system is used whereas in binary subtraction, binary numbers are used for subtraction. The resultant terms can be denoted with the difference and borrow.
Half subtractor is the most essential combinational logic circuit which is used in digital electronics. Basically, this is an electronic device or in other terms, we can say it as a logic circuit. This circuit is used to perform two binary digits subtraction. In the previous article, we have already discussed the concepts of half adder and a full adder circuit which uses binary numbers for the calculation. Similarly, the subtractor circuit uses binary numbers (0,1) for the subtraction. The circuit of the half subtractor can be built with two logic gates namely NAND and EX-OR gates. This circuit gives two elements such as the difference as well as they borrow.
As in binary subtraction, the major digit is 1, we can generate borrow while the subtrahend 1 is superior to minuend 0 and due to this, borrow will need. The following example gives the binary subtraction of two binary bits.
First Digit |
Second Digit | Difference | Borrow |
0 |
0 | 0 | 0 |
1 |
0 | 1 |
0 |
0 | 1 | 1 |
1 |
1 | 1 | 0 |
0 |
In the above subtraction, the two digits can be represented with A and B. These two digits can be subtracted and gives the resultant bits as difference and borrow.
When we observe the first two and fourth rows, the difference between these rows, then the difference and borrow are similar because the subtrahend is lesser than the minuend. Similarly, when we observe the third row, the minuend value is subtracted from the subtrahend. So the difference and borrow bits are 1 because the subtrahend digit is superior to the minuend digit.
This combinational circuit is an essential tool for any kind of digital circuit to know the possible combinations of inputs and outputs. For instance, if the subtractor has two inputs then the resultant outputs will be four. The o/p of the half subtractor is mentioned in the below table that will signify the difference bit as well as borrow bit. The circuit’s truth table explanation can be done by using the logic gates like EX-OR logic gate and AND gate operation followed by NOT gate.
Solving the truth table using K-Map is shown below.
The half subtractor expression using truth table and K-map can be derived as
Difference (D) = (x’y + xy’)
= x ⊕ y
Borrow (B) = x’y
Logical Circuit
The half subtractor logical circuit can be explained by using the logic gates:
- 1 XOR gate
- 1 NOT gate
- 1 AND gate
The representation is
Half-Subtractor Block Diagram
The block diagram of the half subtractor is shown above. It requires two inputs as well as gives two outputs. Here inputs are represented with A&B, and outputs are Difference and Borrow.
The above circuit can be designed with EX-OR & NAND gates. Here, the NAND gate can be build by using AND and NOT gates. So we require three logic gates for making half a subtractor circuit namely the EX-OR gate, NOT gate, and NAND gate.
A combination of AND and NOT gate produce a different combined gate named NAND Gate. The Ex-OR gate output will be the Difference bit and the NAND Gate output will be the Borrow bit for the same inputs A&B.
AND-Gate
The AND-gate is one type of digital logic gate with multiple inputs and a single output and based on the inputs combinations it will perform the logical conjunction. When all the inputs of this gate are high, then the output will be high otherwise the output will be low. The logic diagram of AND gate with truth table is shown below.
NOT Gate
The NOT-gate is one type of digital logic gate with a single input and based on the input the output will be reversed. For instance, when the input of the NOT gate is high then the output will be low. The logic diagram of NOT-gate with the truth table is shown below. By using this type of logic gate, we can execute NAND and NOR gates.
Ex-OR Gate
The Exclusive-OR or EX-OR gate is one type of digital logic gate with 2-inputs & single output. The working of this logic gate depends on the OR gate. If anyone of the inputs of this gate is high, then the output of the EX-OR gate will be high. The symbol and truth table of the EX-OR are shown below.
Half Subtractor Circuit using Nand Gate
The designing of the subtractor can be done by using logic gates like the NAND gate & Ex-OR gate. In order to design this half subtractor circuit, we have to know the two concepts namely difference and borrow.
If we monitor cautiously, it is fairly clear that the variety of operation executed by this circuit which is accurately related to the EX-OR gate operation. Therefore, we can simply use the EX-OR gate for making difference. In the same way, the borrow produced by half adder circuit can be simply attained by using the blend of logic gates like AND- gate and NOT-gate.
This HS can also be designed by using NOR gates where it requires 5 NOR gates for the construction. The circuit diagram half subtractor using NOR gates is shown as:
Truth Table
First Bit |
Second Bit | Difference
(EX-OR Out) |
Borrow
(NAND Out) |
0 |
0 | 0 | 0 |
1 | 0 | 1 |
0 |
0 |
1 | 1 |
1 |
1 | 1 | 0 |
0 |
VHDL and Testbench Code
The VHDL code for half subtractor is explained as follows:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Half_Sub1 is
Port ( a: in STD_LOGIC;
b: in STD_LOGIC;
HS_Diff: out STD_LOGIC;
HS_Borrow: out STD_LOGIC);
end Half_Sub1;
architecture Behavioral of Half_Sub1 is
begin
HS_Diff<=a xor b;
HS_Borrow<=(not a) and b;
The testbench code for HS is explained as below:
LIBRARY IEEE;
USE ieee.std_logic_1164.ALL;
ENTITY HS_tb IS
END HS_tb;
ARCHITECTURE HS_tb OF HS_tb IS
COMPONENT HS
PORT( a : IN std_logic;
b : IN std_logic;
HS_Diff : OUT std_logic;
HS_Borrow : OUT std_logic
);
END COMPONENT;
signal a : std_logic := ‘0’;
signal b : std_logic := ‘0’;
signal HS_Diff : std_logic;
signal HS_Borrow : std_logic;
BEGIN
uut: HS PORT MAP (
a => a,
b => b,
HS_Diff => HS_Diff,
HS_borrow => HS_borrow
);
stim_proc: process
begin
a <= ‘0’;
b <= ‘0’;
wait for 30 ns;
a <= ‘0’;
b <= ‘1’;
wait for 30 ns;
a <= ‘1’;
b <= ‘0’;
wait for 30 ns;
a <= ‘1’;
b <= ‘1’;
wait;
end process;
END;
Full Subtractor Using Half Subtractor
A full subtractor is a combinational device that operates the subtraction functionality by using two bits and is minuend and subtrahend. The circuit considers the borrow the previous output and it has three inputs with two outputs. The three inputs are the minuend, subtrahend and the input received from the previous output which is borrow and the two outputs are the difference and borrow.
The truth table for full subtractor is
Inputs | Outputs | |||
X | Y | Yin | FS_Diff | FS_Borrow |
0 | 0 | 0 | 0 | 0 |
0 | 0 | 1 | 1 | 1 |
0 | 1 | 0 | 1 | 1 |
0 | 1 | 1 | 0 | 1 |
1 | 0 | 0 | 1 | 0 |
1 | 0 | 1 | 0 | 0 |
1 | 1 | 0 | 0 | 0 |
1 | 1 | 1 | 1 | 1 |
With the above truth table, the logical diagram ad circuits diagram for the implementation of full subtractor using half subtractors is shown below:
Advantages and Limitations of Half Subtractor
The advantages of half subtractor are:
- The implementation and construction of this circuit is simple and easy
- This circuit consumes minimal power in digital signal processing
- computational functionalities can be performed at improved speed rates
The limitations of this combinational circuit are:
Even though there are extensive applications of half subtractor in many operations and functionalities, there are few limitations and those are:
- The half subtractor circuits will not accept “Borrow-in” from the previous outputs where this is the crucial drawback of this circuit
- As many real-time applications operate on the subtraction of numerous number of bits, half subtractors devices do not hold any capability of subtracting many bits
Applications of Half Subtractor
The applications of half subtractor include the following.
- Half subtractor is used to reduce the force of audio or radio signals
- It can be used in amplifiers to reduce the sound distortion
- Half subtractor is used in ALU of processor
- It can be used to increase and decrease operators and also calculates the addresses
- Half subtractor is used to subtract the least significant column numbers. For the subtraction of multi-digit numbers, it can be used for the LSB.
Therefore, from the above half subtractor theory, at last, we can close that by using this circuit we can subtract from one binary bit from another to provide the outputs like Difference and Borrow. Similarly, we can design half subtractor using NAND gates circuit as well as NOR gates. The other concepts to be known are what is the half subtractor verilog code and how the RTL schematic diagram can be drawn?